High-performance integrated circuits have traditionally been characterized by the clock frequency at which they operate. Gauging the ability of a circuit to operate at the specified speed requires an ability to measure, during the design process, its delay at numerous steps.
The best source to analyze timing problems on a digital IC is the end point report (EPR), which shows the critical timing path through the circuit from a source pin (launching latch, or, in some cases, the chip input pin) to a target pin (receiving latch, or, in some cases, the chip output pin), including all involved devices and wires. The critical timing path is the path having the maximum delay between a given source pin and a corresponding target pin.
The end point report and the comprehensive timing report (CTR) are the output of a static timing analysis that computes timing data for a circuit. This timing data may be manually analyzed and investigated to find and/or eliminate the reasons for bad timing results. To clearly distinguish static timing analysis that computes timing data and the manual timing analysis that investigates the timing data for the reasons behind timing results, in this document, the term “simulation” is used in reference to static timing analysis and the term “timing analysis” is used in reference to manual timing investigation of the simulation results.
While EPRs are useful for timing analysis, typical EPRs are based on a timing simulation of an IC, which does not add all timing paths through the simulated circuit to the EPR. Conventional EPRs only contain the most critical paths and only contain the path for the most critical bit within a bus. Especially in a hierarchical design, for a subset of the circuit known as the lower hierarchy (also called a “macro”), a timing simulation abstract is created and used for the simulation of the whole circuit.